RISC architecture is going to change everything
It’s really nice to see high end open source hardware becoming a thing.
Well risc-v is a nice open ISA, not open source HW. Even when some companies post the chisel code, or the rtl one on github, doesn’t necessarily make it open source. There are vendors with proprietary risc-v based IP already.
On the other hand really open HW is really hard to happen. The Fabs recipes for different technologies, is like secret sauce. And securing the produced HW vs the chisel/rtl code is really hard, starting form the fact the business ecosystem is mostly fabless (except for Intel and adn a few IDS companies around), and companies designing usually include proprietary IP from vendors (who knows what they add into their IP), so no way to verify that code, and it’s impossible for every company to design everything (too much complexity and too much expertise on a diverse ecosystem of different technologies). Then when having the rtl and gatesims somehow verified, companies send to a 3rd party for the “physical” design, including tracing and routing plus “mask” design, and as long as there’s equivalence between the original design (which already incorporated proprietary IP) and the one send back by the 3rd party company, then it goes to the Fab (though the 3rd party company could have introduced something, obscured somehow so equivalence is not broken), and then finally, even if the Fab doesn’t introduce anything the original company is not aware of, in the end the recipe for whether 14nm, 7nm, 2nm, and everything related to how the company achieves what it does, is not open either (there are of course theory, papers and talks about the processes, but what the Fab finally does, has to be protected against competitors). All the original company can do, is to verify the functionality of the resulting Si, starting from postSi verification all the way down to product verification. But several key pieces were even proprietary IP and libraries to start with, the thing goes through several hands until it lands to the Fab, and what ended in the final Si is not fully known, all you can do is verify under certain scenarios the thing does what it was intended for, :)
So in the end fully open HW is really hard to get. But an open ISA is better than current status quo, and hopefully it might motivate for more openness on the HW industry…
Yeah that’s fair, while base spec is open companies don’t actually publish the exact specs for the actual chips they produce.
I just hope they - somehow - find a solution for the problem that you can’t verify a build as of now. It was apparently not really easy to do with software, but with hardware? It seems almost impossible. But in order to be really sure that what you see is what you get - we need that verification.
Don’t ask me how that would even be possible. Because every solution my buddies and I have thought of is impossible or means to have hardware that is akin to the state of things roughly 50 years ago and extremely slow.
As you mention this is a hard problem. Perhaps there’s some way to create a hardware equivalent of a checksum. I imagine for the foreseeable future it’s going to come down to how much you trust the vendor. One point to note is that there are only a handful of foundries capable of producing advanced chips anyways.
yeah, risc is good
Mips died, Android drops support for MIPS, then RISC-V gets created after MIPS ashes and android adds support for risc-v, correct?
It’s happening!! In a few years we’ll see some risc android phones.
